This book describes how reconfigurable hardware technologies such as field-programmable gate arrays (FPGAs) offer cost-effective, flexible platforms for implementing WMSNs, with a main focus on developing efficient algorithms and architectures for information reduction, including event detection, event compression, and multicamera processing for hardware implementations. The authors include a comprehensive review of wireless multimedia sensor networks, a complete specification of a very low-complexity, low-memory FPGA WMSN node processor, and several case studies that illustrate information reduction algorithms for visual event compression, detection, and fusion.

The book will be of interest to academic researchers, R&D engineers, and computer science and engineering graduate students engaged with signal and video processing, computer vision, embedded systems, and sensor networks.