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Autor(en): 
  • Mourad Debbabi
  • Fawzi Hassaïne
  • Yosr Jarraya
  • Luay Alawneh
  • Andrei Soeanu
  • Verification and Validation in Systems Engineering: Assessing UML/SysML Design Models 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  November 2014  
    Genre:  EDV / Informatik 
     
    C / computer science / Computer system failures / information architecture / IT Operations / Maintenance & repairs / Management information systems / Management of Computing and Information Systems
    ISBN:  9783642423161 
    EAN-Code: 
    9783642423161 
    Verlag:  Springer EN 
    Einband:  Kartoniert  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D  
    Gewicht:  427 gr 
    Seiten:  248 
    Illustration:  XXVI, 248 p. 
    Zus. Info:  EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025. 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle.

    Debbabi and his coauthors investigate methodologies and techniques that can be employed for the automatic verification and validation of systems engineering design models expressed in standardized modeling languages. Their presentation includes a bird's eye view of the most prominent modeling languages for software and systems engineering, namely the Unified Modeling Language (UML) and the more recent Systems Modeling Language (SysML). Moreover, it elaborates on a number of quantitative and qualitative techniques that synergistically combine automatic verification techniques, program analysis, and software engineering quantitative methods applicable to design models described in these modeling languages. Each of these techniques is additionally explained using a case study highlighting the process, its results, and resulting changes in the system design.

    Researchers in academia and industry as well as students specializing in software and systems engineering will find here an overview of state-of-the-art validation and verification techniques. Due to their close association with the UML standard, the presented approaches are also applicable to industrial software development.

      
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