Übersicht			Auf mobile öffnen

Lieferstatus:	Auf Bestellung (Lieferzeit unbekannt)
Veröffentlichung:	August 2013
Genre:	Naturwissensch., Medizin, Technik
	B / Circuits and Systems / Computer architecture & logic design / Electronic circuits / Electronic Circuits and Systems / Electronics / Electronics and Microelectronics, Instrumentation / Electronics engineering / engineering / Microelectronics / Microprocessors / Processor Architectures / Rechnerarchitektur und Logik-Entwurf mehr...
ISBN:	9781461473237
EAN-Code:	9781461473237
Verlag:	Springer EN
Einband:	Gebunden
Sprache:	English
Dimensionen:	H 235 mm / B 155 mm / D
Gewicht:	7096 gr
Seiten:	356
Illustration:	XXXIII, 356 p.
Bewertung:	Titel bewerten / Meinung schreiben

Inhalt:

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ¿have we functionally verified everything¿.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.