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Autor(en): 
  • Weiwei Chen
  • Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  September 2016  
    Genre:  Naturwissensch., Medizin, Technik 
     
    B / Circuits and Systems / Computer architecture & logic design / Electronic circuits / Electronic Circuits and Devices / Electronic Circuits and Systems / Electronic devices & materials / Electronics# circuits & components
    ISBN:  9783319361079 
    EAN-Code: 
    9783319361079 
    Verlag:  Springer EN 
    Einband:  Kartoniert  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D  
    Gewicht:  2642 gr 
    Seiten:  145 
    Illustration:  XIX, 145 p. 51 illus., 41 illus. in color., schwarz-weiss Illustrationen, farbige Illustrationen 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems.  It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time.  Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions.  She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.
     
    . Provides an introduction to electronic system-level (ESL) design, along with background on simulation execution semantics for ESL models;
    . Discusses discrete event simulation, along with synchronous and out-of-order parallel discrete simulation approaches, including the underlying data structure, the scheduling algorithm, and the predictive static code analysis technique;
    . Includes guidelines for choosing among different simulation and diagnosis approaches for models with different features;
    . Presents the model analysis approaches to increase the observability for parallel ESL model development.


      



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