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Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
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Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!
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| This work covers field programmable gate array
(FPGA)-specific optimizations of circuits computing the multiplication of a
variable by several constants, commonly denoted as multiple constant
multiplication (MCM). These optimizations focus on low resource usage but high
performance. They comprise the use of fast carry-chains in adder-based constant
multiplications including ternary (3-input) adders as well as the integration
of look-up table-based constant multipliers and embedded multipliers to get the
optimal mapping to modern FPGAs. The proposed methods can be used for the
efficient implementation of digital filters, discrete transforms and many other
circuits in the domain of digital signal processing, communication and image
processing. Contents -
Heuristic
and ILP-Based Optimal Solutions for the Pipelined Multiple Constant
Multiplication Problem
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Methods to
Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary
(3-Input) Adders
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An Optimized
Multiple Constant Multiplication Architecture Using Floating Point Arithmetic
Target Groups -
Researchers
and students of electrical engineering and computer science
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Practitioners
in the area of FPGAs and signal processing or digital arithmetic
The Author
Martin Kumm
is working as a postdoctoral researcher at the University of
Kassel. His current research interests are digital arithmetic, digital signal
processing and discrete optimization, all in the context of field programmable
gate arrays.
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