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Herausgeber: 
  • Vassilis Paliouras
  • Johan Vounckx
  • Diederik Verkest
  • Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgiu 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  September 2005  
    Genre:  EDV / Informatik 
     
    Algorithms & data structures / Arithmetic and Logic Structures / Arithmetic and logic units, Computer / C / Computer architecture & logic design / computer science / Computer software—Reusability / Computer-Aided Design (CAD) / Computer-aided engineering / Computer-Aided Engineering (CAD, CAE) and Design / Electrical and Electronic Engineering / Electrical Engineering / Hardware Performance and Reliability / Logic Design / Maintenance & repairs / Microprocessors / Performance and Reliability / Processor Architectures / Systems analysis & design
    ISBN:  9783540290131 
    EAN-Code: 
    9783540290131 
    Verlag:  Springer Nature EN 
    Einband:  Kartoniert  
    Sprache:  English  
    Serie:  #3728 - Lecture Notes in Computer Science
    Programming and Software Engineering  
    Dimensionen:  H 235 mm / B 155 mm / D  
    Gewicht:  2360 gr 
    Seiten:  756 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on ¿Traveling the Wild Frontier of Ulta Low-Power Design¿, Dr. Sung Bae Park, S- sung, gave a presentation on ¿DVL (Deep Low Voltage): Circuits and Devices¿, Prof.

      



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