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Autor(en): 
  • Rolf Drechsler
  • Saeideh Shirinzadeh
  • In-Memory Computing: Synthesis and Optimization 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  Juni 2019  
    Genre:  Naturwissensch., Medizin, Technik 
     
    B / Circuits and Systems / Computer architecture & logic design / Electronic circuits / Electronic Circuits and Systems / Electronics / Electronics and Microelectronics, Instrumentation / Electronics engineering
    ISBN:  9783030180256 
    EAN-Code: 
    9783030180256 
    Verlag:  Springer EN 
    Einband:  Gebunden  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D  
    Gewicht:  366 gr 
    Seiten:  115 
    Illustration:  XI, 115 p. 29 illus., 12 illus. in color., schwarz-weiss Illustrationen, farbige Illustrationen 
    Zus. Info:  EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025. 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.

      



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