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Autor(en): 
  • Rolf Drechsler
  • Stephan Eggersglüss
  • High Quality Test Pattern Generation and Boolean Satisfiability 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  Januar 2012  
    Genre:  Naturwissensch., Medizin, Technik 
     
    B / Circuits and Systems / Computer architecture & logic design / Electronic circuits / Electronic Circuits and Systems / Electronics / Electronics and Microelectronics, Instrumentation / Electronics engineering
    ISBN:  9781441999757 
    EAN-Code: 
    9781441999757 
    Verlag:  Springer EN 
    Einband:  Gebunden  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D  
    Gewicht:  488 gr 
    Seiten:  193 
    Illustration:  XVIII, 193 p. 
    Zus. Info:  EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025. 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT).  A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model;Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.
      



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