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Lieferstatus:	Auf Bestellung (Lieferzeit unbekannt)
Veröffentlichung:	Januar 2008
Genre:	EDV / Informatik
	Architecture, Computer / Arithmetic and Logic Structures / Arithmetic and logic units, Computer / C / Compiler und Übersetzer / Compilers & interpreters / Compilers and Interpreters / Computer architecture & logic design / Computer networking & communications / computer science / Computer System Implementation / Distributed databases / Input-output equipment (Computers) / Input/Output and Data Communications / Logic Design / Microprocessors / Processor Architectures / Programming & scripting languages# general / Programming languages (Electronic computers) / Programming Languages, Compilers, Interpreters / Rechnerarchitektur und Logik-Entwurf / Systemanalyse und -design / Systems analysis & design mehr...
ISBN:	9783540775591
EAN-Code:	9783540775591
Verlag:	Springer EN
Einband:	Kartoniert
Sprache:	English
Serie:	#4917 - Lecture Notes in Computer Science Theoretical Computer Science and General Issues
Dimensionen:	H 235 mm / B 155 mm / D
Gewicht:	635 gr
Seiten:	400
Illustration:	XIII, 400 p.
Zus. Info:	EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025.
Bewertung:	Titel bewerten / Meinung schreiben

Inhalt:

Invited Program.- Supercomputing for the Future, Supercomputing from the Past (Keynote).- I Multithreaded and Multicore Processors.- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing.- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect.- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE.- IIa Reconfigurable - ASIP.- BRAM-LUT Tradeoff on a Polymorphic DES Design.- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.- IIb Compiler Optimizations.- Fast Bounds Checking Using Debug Register.- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.- III Industrial Processors and Application Parallelization.- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.- Experiences with Parallelizing a Bio-informatics Program on the Cell BE.- Drug Design Issues on the Cell BE.- IV Power-Aware Techniques.- Coffee: COmpiler Framework for Energy-Aware Exploration.- Integrated CPU Cache Power Management in Multiple Clock Domain Processors.- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.- V High-Performance Processors.- The Significance of Affectors and Affectees Correlations for Branch Prediction.- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator.- LPA: A First Approach to the Loop Processor Architecture.- VI Profiles: Collection and Analysis.- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm.- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy.- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior.- VII Optimizing Memory Performance.- MLP-Aware Dynamic Cache Partitioning.- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory.- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.