Übersicht			Auf mobile öffnen

Lieferstatus:	Auf Bestellung (Lieferzeit unbekannt)
Veröffentlichung:	Oktober 2014
Genre:	Naturwissensch., Medizin, Technik
	B / Circuits and Systems / Computer-Aided Design (CAD) / Computer-aided engineering / Computer-Aided Engineering (CAD, CAE) and Design / Electronic circuits / Electronic Circuits and Systems / engineering / Microelectronic Systems / model checking / System Level Design / System Level Verification mehr...
ISBN:	9781493901012
EAN-Code:	9781493901012
Verlag:	Springer EN
Einband:	Kartoniert
Sprache:	English
Dimensionen:	H 235 mm / B 155 mm / D
Gewicht:	291 gr
Seiten:	167
Illustration:	XIII, 167 p.
Zus. Info:	EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025.
Bewertung:	Titel bewerten / Meinung schreiben

Inhalt:

This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers. ? The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification; Uses a combination of formal techniques to do scalable verification of system designs completely automatically; Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-levelRTL; Written by researchers working in mainstream hardware and software design and includes results from both academia and industry ? ? ?