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Autor(en): 
  • Liang Liu
  • Viktor Öwall
  • Chenxin Zhang
  • Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing: From Algorithm to Architecture 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 2 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  Januar 2016  
    Genre:  Naturwissensch., Medizin, Technik 
     
    B / Circuits and Systems / Computer Architecture / Computer architecture and logic design / Electronic Circuits and Systems / Electronics / Electronics and Microelectronics, Instrumentation / Electronics engineering
    ISBN:  9783319240022 
    EAN-Code: 
    9783319240022 
    Verlag:  Springer EN 
    Einband:  Gebunden  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D 17 mm 
    Gewicht:  489 gr 
    Seiten:  195 
    Illustration:  XIV, 195 p. 81 illus., 29 illus. in color., schwarz-weiss Illustrationen, farbige Illustrationen 
    Zus. Info:  EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025. 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G.


    .Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration;

    .Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support;

    .Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications.


      



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