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Digital System Test and Testable Design: Using HDL Models and Architectures
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Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!
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| Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate
Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns
Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods |
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