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Autor(en): 
  • Kees Goossens
  • Bart Vermeulen
  • Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 3 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  August 2014  
    Genre:  Naturwissensch., Medizin, Technik 
     
    B / Circuits and Systems / Computer architecture & logic design / Electronic circuits / Electronic Circuits and Systems / Electronics / Electronics and Microelectronics, Instrumentation / Electronics engineering
    ISBN:  9783319062419 
    EAN-Code: 
    9783319062419 
    Verlag:  Springer EN 
    Einband:  Gebunden  
    Sprache:  English  
    Serie:  Embedded Systems  
    Dimensionen:  H 235 mm / B 155 mm / D  
    Gewicht:  6151 gr 
    Seiten:  311 
    Illustration:  XV, 311 p. 127 illus., 7 illus. in color., schwarz-weiss Illustrationen, farbige Illustrationen 
    Zus. Info:  EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025. 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly. Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors. The authors' novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug flow to be used during the design of an SOC, and customizable off-chip debugger software. Coverage includes an evaluation of the efficiency and effectiveness of the CSAR approach and its supporting infrastructure, using six industrial SOCs and an illustrative, example SOC model. The authors also quantify the hardware cost and design effort to support their approach.
     

      



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