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Autor(en): 
  • Harry A. G. Wijshoff
  • Data Organization in Parallel Computers 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 2 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   i.d.R. innert 14-24 Tagen versandfertig
    Veröffentlichung:  Oktober 2011  
    Genre:  Naturwissensch., Medizin, Technik 
     
    COMPUTERS / Hardware / Mainframes & Minicomputers / COMPUTERS / Systems Architecture / General / GARDENING / General
    ISBN:  9781461289647 
    EAN-Code: 
    9781461289647 
    Verlag:  Springer Nature B.V. 
    Einband:  Kartoniert  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D 15 mm 
    Gewicht:  406 gr 
    Seiten:  264 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    The organization of data is clearly of great importance in the design of high performance algorithms and architectures. Although there are several landmark papers on this subject, no comprehensive treatment has appeared. This monograph is intended to fill that gap. We introduce a model of computation for parallel computer architec­ tures, by which we are able to express the intrinsic complexity of data or­ ganization for specific architectures. We apply this model of computation to several existing parallel computer architectures, e.g., the CDC 205 and CRAY vector-computers, and the MPP binary array processor. The study of data organization in parallel computations was introduced as early as 1970. During the development of the ILLIAC IV system there was a need for a theory of possible data arrangements in interleaved mem­ ory systems. The resulting theory dealt primarily with storage schemes also called skewing schemes for 2-dimensional matrices, i.e., mappings from a- dimensional array to a number of memory banks. By means of the model of computation we are able to apply the theory of skewing schemes to var­ ious kinds of parallel computer architectures. This results in a number of consequences for both the design of parallel computer architectures and for applications of parallel processing.

      



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