Übersicht			Auf mobile öffnen

Lieferstatus:	Auf Bestellung (Lieferzeit unbekannt)
Veröffentlichung:	November 2007
Genre:	Naturwissensch., Medizin, Technik
	B / Circuits and Systems / Computer-Aided Design (CAD) / Computer-aided engineering / Computer-Aided Engineering (CAD, CAE) and Design / Electrical and Electronic Engineering / Electrical Engineering / Electronic circuits / Electronic Circuits and Systems / Elektrotechnik / engineering mehr...
ISBN:	9780387366418
EAN-Code:	9780387366418
Verlag:	Springer EN
Einband:	Gebunden
Sprache:	English
Serie:	Integrated Circuits and Systems
Dimensionen:	H 235 mm / B 155 mm / D 23 mm
Gewicht:	670 gr
Seiten:	318
Illustration:	XVIII, 318 p.
Zus. Info:	EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025.
Bewertung:	Titel bewerten / Meinung schreiben

Inhalt:

A project's functional verification testplan is the specification for the verification process. Developing this testplan usually involves the entire engineering team (architects, designers, and verification engineers). This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. This is the first book published on this subject. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions. Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP.