Übersicht			Auf mobile öffnen

Lieferstatus:	Auf Bestellung (Lieferzeit unbekannt)
Veröffentlichung:	September 2013
Genre:	Naturwissensch., Medizin, Technik
	B / Circuits and Systems / Computer architecture & logic design / Digital and Analog Signal Processing / Electronic circuits / Electronic Circuits and Systems / engineering / Image processing / Imaging systems & technology / Microprocessors / Processor Architectures / Rechnerarchitektur und Logik-Entwurf / Signal Processing / Signal, Image and Speech Processing / Speech processing systems mehr...
ISBN:	9783319011493
EAN-Code:	9783319011493
Verlag:	Springer EN
Einband:	Gebunden
Sprache:	English
Serie:	#121 - Analog Circuits and Signal Processing
Dimensionen:	H 235 mm / B 155 mm / D
Gewicht:	4293 gr
Seiten:	162
Illustration:	XVI, 162 p. 166 illus., 68 illus. in color., farbige Illustrationen, schwarz-weiss Illustrationen
Zus. Info:	EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025.
Bewertung:	Titel bewerten / Meinung schreiben

Inhalt:

This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis.  Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.