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Autor(en): 
  • Nuno Horta
  • Nuno Lourenço
  • Ricardo Martins
  • Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques 
     

    (Buch)
    Dieser Artikel gilt, aufgrund seiner Grösse, beim Versand als 2 Artikel!


    Übersicht

    Auf mobile öffnen
     
    Lieferstatus:   Auf Bestellung (Lieferzeit unbekannt)
    Veröffentlichung:  Mai 2018  
    Genre:  Naturwissensch., Medizin, Technik 
     
    B / Circuits and Systems / Computer architecture & logic design / Electronic circuits / Electronic Circuits and Systems / Electronics / Electronics and Microelectronics, Instrumentation / Electronics engineering
    ISBN:  9783319816685 
    EAN-Code: 
    9783319816685 
    Verlag:  Springer EN 
    Einband:  Kartoniert  
    Sprache:  English  
    Dimensionen:  H 235 mm / B 155 mm / D 12 mm 
    Gewicht:  349 gr 
    Seiten:  207 
    Illustration:  XVI, 207 p. 108 illus., 79 illus. in color., farbige Illustrationen, schwarz-weiss Illustrationen 
    Zus. Info:  EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025. 
    Bewertung: Titel bewerten / Meinung schreiben
    Inhalt:
    This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.
    • Introduces readers to hierarchical combination of Pareto fronts of placements;
    • Presents electromigration-aware routing with multilayer multiport terminal structures;
    • Includes evolutionary multi-objective multi-constraint detailed Router;
    • Enables parasitic extraction performed over a semi-complete layout.
      



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