Übersicht			Auf mobile öffnen

Lieferstatus:	Auf Bestellung (Lieferzeit unbekannt)
Veröffentlichung:	November 2010
Genre:	Naturwissensch., Medizin, Technik
	B / Circuits and Systems / Computer architecture & logic design / Computer architecture and logic design / Computer Engineering and Networks / computer hardware / Computer memory systems / Computer networking & communications / Computer organization / Computer Systems Organization and Communication Networks / Computerhardware / Electronic circuits / Electronic Circuits and Systems / engineering / Memory Structures / Microprocessors / Processor Architectures / Rechnerarchitektur und Logik-Entwurf / Storage media & peripherals mehr...
ISBN:	9789048173884
EAN-Code:	9789048173884
Verlag:	Springer EN
Einband:	Kartoniert
Sprache:	English
Dimensionen:	H 235 mm / B 155 mm / D
Gewicht:	391 gr
Seiten:	229
Illustration:	XIX, 229 p.
Zus. Info:	EUDR exemption - product or manufacturing materials placed on the market prior to 31.12.2025.
Bewertung:	Titel bewerten / Meinung schreiben

Inhalt:

In Co-Design for System Acceleration , we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-designsystem for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.